FIG. 1 shows the architecture of an exemplary multi-core processor 100. As observed in FIG. 1, the processor includes: 1) multiple processing cores 101_1 to 101_N; 2) an interconnection network 102; 3) a last level caching system 103; 4) a memory controller 104 and an I/O hub 105. Each of the processing cores contain one or more instruction execution pipelines for executing program code instructions. The interconnect network 102 serves to interconnect each of the cores 101_1 to 101_N to each other as well as the other components 103, 104, 105. The last level caching system 103 serves as a last layer of cache in the processor before instructions and/or data are evicted to system memory 106.
The memory controller 104 reads/writes data and instructions from/to system memory 106. The I/O hub 105 manages communication between the processor and “I/O” devices (e.g., non volatile storage devices and/or network interfaces). Port 107 stems from the interconnection network 102 to link multiple processors so that systems having more than N cores can be realized. Graphics processor 108 performs graphics computations. Power management circuitry 109 manages the performance and power states of the processor as a whole (“package level”) as well as aspects of the performance and power states of the individual units within the processor such as the individual cores 101_1 to 101_N, graphics processor 108, etc. Other functional blocks of significance (e.g., phase locked loop (PLL) circuitry) are not depicted in FIG. 1 for convenience.
As the power consumption of computing systems has become a matter of concern, most present day systems include sophisticated power management functions. A common framework is to define both “performance” states and “power” states. The entry and/or departure from any one of these states may be controlled, for example, by power management circuitry 109. The performance of a block of logic corresponds to its ability to do work over a set time period. That is, the higher the logic block's performance the more work it can do over the set time period. Here, the primary factor that determines the logic block's performance, for a fixed configuration of the logic block, is its frequency of operation. Specifically, the higher the clock frequency applied to the logic block, the higher its performance will be. Typically, in order to operate correctly at higher frequencies, the logic block's supply voltage also needs to be raised. Both the clock speed and supply voltage level can be adjusted during runtime, e.g., by power management circuitry 109.
Another factor that can affect the logic block's performance is how many of its internal units that can do work are enabled. For example, a typical graphics processor 108 has a plurality of internal execution cores 120_1 to 120_Z each of which are designed to actually execute the snippets of graphics program code that represent the images rendered on a computer display. Usually, the graphics processor 108 is designed to support different configurations of operation that correspond to different numbers of enabled execution cores. For example, a first configuration might have all of the execution cores 120_1 to 120_Z enabled and another configuration might have only half the internal cores enabled. The number of enabled cores also affects the processor's ability to do work and therefore also affects its performance. The actual “performance” of a graphics processor is therefore a complicated mixture of the number of enabled cores and the frequency of the clock signal applied to the cores.
Adding to the complexity, unfortunately, is the reality that the power consumption of a logic block increases along with its frequency and performance.